View DS1822ZTR_8903272.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

benefits and features ? unique 1 - wire ? i nterface r equires o nly one p ort p in for communications o can be powered from data line o power -supply range is 3.0v to 5.5v ? reduced component count with integrated temperature sensor and interface o requires no external components o measures temperatures from - 55c to +125c (-67f to +257f) o 2.0 c accuracy from -10c to +85c o thermometer resolution is user - selectable from 9 to 12 bits o converts t emperature to 12 -b it d igital w ord in 750ms (max ) ? simplifies distributed te mperature sensing with multidrop capability o each device has a unique 64 - bit serial code stored in an on- board device o flexible, user - definable nonvolatile (nv) a larm s ettings with alarm s earch command i dentifies devices with temperatures outside program med limits o software compatible with the ds18b20 ? applications i nclude t hermostatic controls, industrial s ystems, consumer products, t hermometers, or a ny t hermally s ensitive system pin assignment pin description gnd - ground dq - data in/out v dd - power supply voltage nc - no connect description the ds1822 digital thermometer provides 9 - to 12 - bit centigrade temperature measurements and has an alarm function with nv user - programmable upper and lower trigger points. the ds182 2 communicates over a 1- wire bus that by definition requires only one data line (and ground) for communicati on with a central microprocessor. it has an operating temperature range of C 55c to +125c and is accurate to 2.0 c over the range of C 10c to +85 c . in addition, the ds1822 can derive power directly from the data line (parasite power), eliminating the need for an external power supply . each ds1822 has a unique 64 - bit serial code, which allows multiple ds1822s to function on the 1- wire bus; thus, it is simple to use one microprocessor to control many ds1822s distributed over a la rge area. applications that can benefit from this feature include hvac environmental contr ols, temperature monitoring systems inside buildings, equipment or machinery, and process monitoring and control systems. 1 (bottom view) 2 3 ds1822 econo 1 - wire digital thermometer 8-pin 150mil so (ds1822z) to -92 (ds1822) dallas 1822 1 gnd dq v dd 2 3 nc nc nc nc gnd dq v dd nc 6 8 7 5 3 1 2 4 ds1822 1- wire is a registered trademark of maxim integrated products, inc . 1 of 21 042815 downloaded from: http:///
ds1822 order information ordering number package marking description ds1822 1822 ds1822 in 3-pin to92 ds1822/t&r 1822 ds1822 in 3-pin to92, 2000 piece tape- and - reel ds1822+ 1822 (see note) ds1822 in lead- free 3 -pin t o92 ds1822+t&r 1822 (see note) ds1822 in lead- free 3 -pin to92, 2000 piece tape- and - reel ds1822z ds1822 ds1822 in 150 mil 8- pin so ds1822z/t&r ds1822 ds1822 in 150 mil 8-pin so, 2500 piece tape- and - reel ds1822z+ ds1822 (see note) ds1822 in lead- free 150 mil 8 -pin so ds1822z+t&r ds1822 (see note) ds1822 in lead - free 150 mil 8 - pin so, 2500 piece tape - and - reel note: a + symbol will also be marked on the package. detailed pin descrip tions table 1 8- pin so* to -92 symbol description 5 1 gnd ground. 4 2 dq data input/output pin. open -drain 1- wire interface pin. also provides power to the device when used in parasite power mode (see parasite power section). 3 3 v dd optional v dd pin. v dd must be grounded for operation in parasite power mode. *all pins not specified in this table are no connect pins. overview figure 1 shows a block diagram of the ds1822, and pin descriptions are given in table 1. the 64 - bit rom stores the devices unique serial code. the scratchpad memory contains t he 2 - byte temperat ure register that stores the digital output from the temperature sensor. in addit ion, the scratchpad provides access to the 1 - byte upper and lower alarm trigger registers (t h and t l ), and the 1 - byte configuration register. the configuration register allows the user to set the resolution of the temperature - to - digital conversion to 9, 10, 11, or 12 bits. the t h , t l and configuration registers are nv (eeprom), so they will retain data when the device is powered down. the ds1822 uses dallas exclusive 1 - wire bu s protocol that implements bus communication using one control signal. the control line requires a weak pullup resistor since all d evices are linked to the bus via a 3- state or open - drain port (the dq pin in the case of the ds1822). in this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each devices unique 64 - bit code. because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. the 1 - wire bus protocol, including detailed explanations of the commands and time slots, is covered in the 1- wire bus system section of this data sheet. another feature of the ds1822 is the ability to operate without an external power suppl y. power is instead supplied through the 1 - wire pullup resistor via the dq pin when the bus is high. the high bus signal also charges an internal capacitor (c pp ), which then supplies power to the device when the bus is low. this method of deriving power from the 1 - wire bus is referred to as parasite power. as an alternative, the ds1822 may also be powered by an external supply on v dd . 2 of 21 downloaded from: http:///
ds1822 ds1822 block diagram figure 1 v pu 4.7k power supply sense 64 - bit rom and 1- wire port dq v dd internal v dd c pp parasite power circuit memory control logic scratchpad 8- bit crc generator temperature sensor alarm high trigger (t h ) register (eeprom) alarm low trigger (t l ) register (eeprom) configuration register (eeprom) gnd ds1822 3 of 21 downloaded from: http:///
ds1822 operation measuring temperature the core functionality of the ds1822 is its direct - to - digital temperature sensor. the resolution of the temperature sensor is user - configurable to 9, 10, 11, or 12 bits, corresponding to increments of 0.5 c, 0.25 c, 0.125 c, and 0.0625 c, respectively. the default resolution at power - up is 12 bit. the ds1822 powers- up in a low -p ower idle state; to initiate a temperature measurement and a - to - d conversion, the master must issue a convert t [44h] command. following the conversion, the resulting thermal data is stored in the 2 - byte temperature register in the scratchpad memory and th e ds1822 returns to its idle state. if the ds1822 is powered by an external supply, the master can issue read - time slots (see the 1 - wire bus system section) after the convert t command and the ds1822 will respond by transmitting 0 while the temperature c onversion is in progress and 1 when the conversion is done. if the ds1822 is powered with parasite power, this notification technique cannot be used since the bus must be pulled high by a strong pullup during the entire temperature conversion. the bus requ irements for parasite power are explained in detail in the powering the ds1822 section of this data shee t. the ds1822 output temperature data is calibrated in degrees centigrade; for fahre nheit applications, a lookup table or conversion routine must be use d. the temperature data is stored as a 16 - bit sign - extended twos complement number in the temperature register (see figure 2). the sig n bits (s) indicate if the temperature is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. if the ds1822 is configured for 12 - bit resolution, all bits in the temperature register will contain valid data. for 11- bit resolution, bit 0 is undefined. for 10 - bit resolution, bits 1 and 0 are undefined, and for 9 - bit resolution bits 2, 1 and 0 are un defined. table 2 gives examples of digital output data and the corresponding temperature reading for 12-bit resolution conversions. temperature register format figure 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte s s s s s 2 6 2 5 2 4 temperature/data relationship table 2 temperature digital output (binary) digital output (hex) +125c 0000 0111 1101 0000 07d0h +85c* 0000 0101 0101 0000 0550h +25.0625c 0000 0001 1001 0001 0191h +10.125c 0000 0000 1010 0010 00a2h +0.5c 0000 0000 0000 1000 0008h 0c 0000 0000 0000 0000 0000h -0.5c 1111 1111 1111 1000 fff8h -10.125c 1111 1111 0101 1110 ff5eh -25.0625c 1111 1110 0110 1111 fe6fh -55c 1111 1100 1001 0000 fc90h *the power on reset value of the temperature register is +85c 4 of 21 downloaded from: http:///
ds1822 operation alarm signaling after the ds1822 performs a temperature conversion, the temperature value i s compared to the user - defined twos complement alarm trigger values stored in the 1 - byte t h and t l registers (see figure 3). the sign bit (s) indicates if the value is positive or negative: for positive numbers s = 0 and for negative numbers s = 1 . the t h and t l registers are nv (eeprom) so they will retain data when the de vice is powered down. t h and t l can be accessed through bytes 2 and 3 of the scratchpad as explained in the memory section of this data sheet. t h and t l register format figure 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 onl y bits 11 through 4 of the temperature register are used in the t h and t l comparison since t h and t l are 8 - bit registers. if the measured temperature is lower than or equal to t l or higher than or equal to t h , an alarm condition exists and an alarm flag is set inside the ds1822. this flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag w ill be turned off after the next temperature conversion. the master device can check the alarm flag status of all ds18 22s on the bus by issuing an alarm search [ech] command. any ds1822s with a set alarm flag will respond to the command, so the ma ster can determine exactly which ds1822s have experienced an alarm condition. if an alarm c ondition exists and the t h or t l set tings have changed, another temperature conversion should be done to validate the alarm condition. powering the ds1822 the ds1822 can be powered by an external supply on the v dd pin, or it can operate in parasite power mode, which allows the ds1822 to function without a local external supply. parasite po wer is very useful for applications that require remote temperature sensing or that are very spac e constrained. figure 1 shows the ds1822s parasite - power control circuitry, which steals power from the 1- wire bus via the dq pin when the bus is high. the stolen charge powers the ds1822 while the bus is high, and some of the charge is stored on the parasite power capacitor (c pp ) to provide power when the bus is low. when the ds1822 is used in parasite power mode, the v dd pin must be connected to ground. in parasite power mode, the 1 - wire bus and c pp can provide sufficient current to the ds1822 for most operations as long as the specified timing and voltage requirements are met (ref er to the dc electrical c haracteristics and the ac electrical characteristics sections of thi s data sheet). however, when the ds1822 is performing temperature conversions or copying data from the scratchpad memory to eeprom, the operating current can be as high as 1.5ma. this curr ent can cause an unacceptable voltage drop across the weak 1 - wire pullup resistor and is more current than can be supplied by c pp . to assure that the ds1822 has sufficient supply current, it is necessary to provide a strong pullup on the 1 - wire bus wheneve r temperature conversions are taking place or data is being copied from the scratchpad to eeprom. this can be accomplished by using a mosfet t o pull the bus directly to the rail as shown in figure 4. the 1 - wire bus must be switched to the strong pullup wit hin 10 s (max) after a convert t [44h] or copy scratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (t conv ) or data transfer (t wr = 10ms). no other activity can take place on the 1 -wire bus while the pullup is enabled. the ds1822 can also be powered by the conventional method of connecting an external powe r supply to the v dd pin, as shown in figure 5. the advantage of this method is that the mosfet pullup is not required, and the 1- wire bus is free to carry other traffic during the temperature conversion time. 5 of 21 downloaded from: http:///
ds1822 the use of parasite power is not recommended for temperatures above 100 c since the ds1822 may not be able to sustain communications due to the higher leakage currents that can exis t at these temperatures. for applications in which such temperatures are likely, it is strongly recomm ended that the ds1822 be powered by an exter nal power supply. in some situations the bus master may not know whether the ds1822s on the bus are parasite powered or powered by external supplies. the master needs this information to determine i f the strong bus pullup should be used during temperature conversions. to get this information, the master can i ssue a skip rom [cch] command followed by a read power supply [ b4h ] command followed by a read - time slot. during the read time slot, parasite powered ds1822s will pull the bus low, and externa lly powe red ds1822s will let the bus remain high. if the bus is pulled low, the master knows that it m ust supply the strong pullup on the 1-wire bus during temperature conversions. supplying the parasite - powered ds1822 during temperature conversions figure 4 powering the ds1822 with an external supply figure 5 64 - bit lasered rom code each ds1822 contains a unique 64 C bit code (see figure 6) stored in rom. the least significant 8 bits of the rom code contain the ds1822s 1 - wire family code : 22h. the next 48 bits contain a unique serial number. the most significant 8 bits contain a cyclic redundancy check (crc) byte that is calculated from the first 56 bits of the rom code. a detailed explanation of the crc bits is provided in the crc genera tion section. the 64 - bit rom code and associated rom function control logic allow the ds1822 to operate as a 1 - wire device using the protocol detailed in the 1 - wire bus system section of this data sheet. 64 - bit lasered rom code figure 6 8- bit crc 48- bit serial number 8- bit family code (22h) msb msb lsb lsb lsb msb v dd (external supply) ds1822 gnd v dd dq v pu 4.7k to other 1- wire devices 1- wire bus micro - processor v pu v pu 4.7k 1- wire bus micro - processor ds1822 gnd v dd dq to other 1- wire devices 6 of 21 downloaded from: http:///
ds1822 memory the ds1822s memory is organized as shown in figure 7. the memory consists of an sram scr atchpad with nv eeprom storage for the high and low alarm trigger registers (t h and t l ) and configuration register. not e that if the ds1822 alarm function is not used, the t h and t l registers can serve as general - purpose memory. all memory commands are described in detail in the ds1822 function commands section. byte 0 and byte 1 of the scratchpad contain the lsb and the m sb of the temperature register, respectively. these bytes are read - only. bytes 2 and 3 provide access to t h and t l registers. byte 4 contains the configuration register data, which is explained in detail in the configuration register section of this data s heet. bytes 5, 6, and 7 are reserved for internal use by the device and cannot be overwritten. byte 8 of the scratchpad is read - only and contains the cyclic redundancy check (crc) code for bytes 0 through 7 of the scratchpad. the ds1822 generates this crc using the method described in the crc generation section. data is written to bytes 2, 3, and 4 of the scratchpad using the write scratchpad [4eh] command; the data must be transmitted to the ds1822 starting with the least significant bit of byte 2. to v erify data integrity, the scratchpad can be read (using the read scratchpad [beh] command) after the dat a is written. when reading the scratchpad, data is transferred over the 1 - wire bus starting with the least significant bit of byte 0. to transfer the t h , t l and configuration data from the scratchpad to eeprom, the master must issue the copy scratchpad [48h] command. data in the eeprom registers is retained when the device is powered down; a t power - up the eeprom d ata is reloaded into the corresponding scratchpad locations. data can also be rel oaded from eeprom to the scratchpad at any time using the recall e 2 [b8h] command. the master can issue read time slots following the recall e 2 command and the ds1822 will ind icate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. ds1822 memory map figure 7 scratchpad (power - up state) byte 0 temperature lsb (50h) byte 1 temperature msb (05h) eeprom byte 2 t h r egister or user byte 1* t h register or user byte 1 byte 3 t l register or user byte 2* t l register or user byte 2 byte 4 configuration register* configuration register byte 5 reserved (ffh) byte 6 reserved byte 7 reserved (10h) byte 8 c rc* * power - up state depends on value(s) stored in eeprom (85c) 7 of 21 downloaded from: http:///
ds1822 configuration regist er byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in figure 8. the user can set the conversion resolution of the ds1822 using the r0 and r1 bits in this register as shown in table 3. the power - up default of these bits is r0 = 1 and r1 = 1 (12 - bit resolution). note that there is a direct tradeoff between resolution and conversion t ime. bit 7 and bits 0 C 4 in the configur ation register are reserved for internal use by the device and cannot be overwr itten . configuration register figure 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 r1 r0 1 1 1 1 1 thermometer resolution configu ration table 3 r1 r0 resolution max conversion time 0 0 9-bit 93.75ms (t conv /8) 0 1 10-bit 187.5ms (t conv /4) 1 0 11-bit 375ms (t conv /2) 1 1 12-bit 750ms (t conv ) crc generation crc bytes are provided as part of the ds1822s 64 - bit rom code and in the 9 th byte of the scratchpad memory. the rom code crc is calculated from the first 56 bits of the rom code and i s contained in the most significant byte of the rom. the scratchpad crc is calculated from the data stored in the scratchpad, and therefore it ch anges when the data in the scratchpad changes. the crcs provide the bus master with a method of data validation when data is read from the ds1822. to verify that da ta has been read correctly, the bus master must recalculate the crc from the received data a nd then compare this value to either the rom code crc (for rom reads) or to the scratchpad crc (for scratchpad reads). if the calculated crc matches the read crc, the data has been received error free. the compa rison of crc values and the decision to continue with an operation are determined entirely by the bus ma ster. there is no circuitry inside the ds1822 that prevents a command sequence from proceeding if the ds 1822 crc (rom or scratchpad) does not match the value generated by the bus master. the equivalent polynomial function of the crc (rom or scratchpad) is: crc = x 8 + x 5 + x 4 + 1 the bus master can recalculate the crc and compare it to the crc values from the ds 1822 using the polynomial generator shown in figure 9. this circuit consists of a shift register and xor gates, and the shift register bits are initialized to 0. starting with the least significant bit of the ro m code or the least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the s hift register. after shi fting in the 56 th bit from the rom or the most significant bit of byte 7 from the scratchpad, the polynomial generator will contain the recalculated crc. next, the 8 - bit rom code or scratchpad crc from the ds1822 must be shifted into the circuit. at this p oint, if the recalculated crc was correct, the shift register will contain all 0s. additional information about the dallas 1 - wire cyclic redundancy check 8 of 21 downloaded from: http:///
ds1822 is available in application note 27 entitled understanding and using cyclic redundancy checks with dal las semiconductor touch memory products . crc generator figure 9 1- wire bus system the 1 - wire bus system uses a single bus master to control one or more slave devices. the d s1822 is always a slave. when there is only one slave on the bus, the syst em is referred to as a single -drop system; the system is multidrop if there are multiple slaves on the bus. all data and commands are transmitted least significant bit first over the 1 -wire bus. the following discussion of the 1 - wire bus system is bro ken down into three topics: hardware configuration, transaction sequence, and 1- wire signaling (signal types and timing). hardware configuration the 1 - wire bus has by definition only a single data line. each device (master or slave) interfaces to the data line via an open drain or 3 - state port. this allows each device to release the data line when the device is not transmitting data so the bus is available for use by another device. t he 1 - wire port of the ds1822 (the dq pin) is open drain with an internal circuit equivalent to that shown in figur e 10. the 1 - wire bus requires an external pullup resistor of approximately 5 k ? ; thus, the idle state for the 1 - wire bus is high. if for any reason a transaction needs to be suspended, the bus mus t be left in the idle state if the transaction is to resume. infinite recovery time can occur between b its so long as the 1 - wire bus is in the inactive (high) state during the recovery period. if the bus is held low f or more than 480 s, all components on the bus will be reset. hardware configuration figure 10 (msb) (lsb) xor xor xor input v pu 4.7k 5a typ. r x t x ds1822 1- wire port 100 ? mosfet t x r x r x = receive t x = transmit 1- wire bus dq pin 9 of 21 downloaded from: http:///
ds1822 transaction sequence the transaction sequence for accessing the ds1822 is as follows: step 1. initialization step 2. rom command (followed by any required data exchange) step 3. ds1822 function c ommand (followed by any required data exchange) it is very important to follow this sequence every time the ds1822 is accessed, a s the ds1822 will not respond if any steps in the sequence are missing or out of order. exceptions to this rule are the search rom [f0h] and alarm search [ech] commands. after issuing either of these ro m commands, the master must return to step 1 in the sequence. initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by prese nce pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that slave devices (s uch as the ds1822) are on the bus and are ready to operate. timing for the reset and presence pulses is detailed in the 1- wire signaling section. rom commands after the bus master has detected a presence pulse, it can issue a rom command. these com mands operate on the unique 64 C bit rom codes of each slave device and allow the ma ster to single out a specific device if many are present on the 1 - wire bus. these commands also allow the master to determine how many and what types of devices are present on the bus or if any device h as experienced an alarm condition. there are five rom commands, and each command is 8 bits long. the master device must issue an appropriate rom command before issuing a ds1822 function command. a flowchart for operation of the rom commands is shown in figure 11. search rom [f0h] when a system is initially po wered up, the master must identify the rom codes of all slave devices on the bus, which allows the master to determine the number of slaves and their device type s. the master learns the rom codes through a process of elimination that requires the master to perform a search rom cycle (i.e., search rom command followed by data exchange) as many times as necess ary to identify all of the slave devices. if there is only one slave on the bus, the simpler read rom command (see below) can be used in place of the search rom process. for a detailed explanation of the search rom procedure, refer to the i button book of standards at www.ibutton.com/ibuttons/standard.pdf . after every search rom cycle, the bus master must return to step 1 (initialization) in the tran sactio n sequence. read rom [33h] this command can only be used when there is one slave on the bus. it allows the bus master to re ad the slaves 64 - bit rom code without using the search rom procedure. if this command is used when there is more than one slave pres ent on the bus, a data collision will occur when all the slaves attempt to respond at the same time. match rom [55h] the match rom command followed by a 64 - bit rom code sequence allows the bus master to address a specific slave device on a multidrop or si ngle - drop bus. only the slave that exactly matches the 64 - bit rom code sequence will respond to the function command issued by the master; all ot her slaves on the bus will wait for a reset pulse. 10 of 21 downloaded from: http:///
ds1822 skip rom [cch] the master can use this command to address all devices on the bus simultaneously wit hout sending out any rom code information. for example, the master can make all ds1822s on the bus perf orm simultaneous temperature conversions by issuing a skip rom command followed by a conver t t [44h] command. no te that the read scratchpad [beh] command can follow the skip rom command only if ther e is a single slave device on the bus. in this case time is saved by allowing the mast er to read from the slave without sending the devices 64 - bit rom code. a skip rom command followed by a read scratchpad command will cause a data collision on the bus if there is more than one slave sinc e multiple devices will attempt to transmit data simultaneously. alarm search [ech] the operation of this command is identical to the op eration of the search rom command except that only slaves with a set alarm flag will respond. this command allows the master dev ice to determine if any ds1822s experienced an alarm condition during the most recent temperature convers ion. after every alarm search cycle (i.e., alarm search command followed by data exchange), the bus mas ter must return to step 1 (initialization) in the transaction sequence. refer to the operation alarm signaling section for an explanation of alarm flag operation. ds1822 function commands after the bus master has used a rom command to address the ds1822 with which it wishe s to communicate, the master can issue one of the ds1822 function commands. these commands allow t he master to write to and read from the ds1822s scratchpad memory, initiate tempe rature conversions and determine the power supply mode. the ds1822 function commands, which are described below, ar e summarized in table 4 and illustrated by the flowchart in figure 12. convert t [44h] this command initiates a singl e temperature conversion. following the conversion, the resulting thermal data is stored in the 2 - byte temperature register in the scratchpad memory and the ds1822 returns to its low- power idle state. if the device is being used in parasite power mode, within 10 s (max) after this command is issued the master must enable a strong pullup on the 1 - wire bus for the duration of the conversion (t conv ) as described in the powering the ds1822 section. if the ds1822 is powered by an external supply, the master can issue read time slots after the convert t command and the ds1822 will respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion is done. in parasite power mode this notification technique cannot be used since the bus is pull ed high by the strong pullup during the conversion. write scratchpad [4eh] this command allows the master to write three bytes of data to the ds1822s scratchpad. the first data byte is written into the t h register (byte 2 of the scratchpad), the second byte is written into the t l register (byte 3), and the third byte is written into the configuration regist er (byte 4). data must be transmitted least significant bit first. all three bytes must be written before the ma ster issues a reset, or the data may be corrupted. read scratchpad [beh] this command allows the master to read the contents of the scratchpad. the data transfer starts with the least significant bit of byte 0 and continues through the scratchpad until the 9 th byte (byte 8 C crc) is read . the master may issue a reset to terminate reading at any time if only part of the s cratchpad data is needed. copy scratchpad [48h] this command copies the contents of the scratchpad t h , t l and configuration registers (bytes 2, 3, and 4) to eeprom. if the device is being used in parasite power mode, within 10 s (max) after this command is 11 of 21 downloaded from: http:///
ds1822 issued the master must enable a strong pullup on the 1 - wire bus for at least 10ms as described in the powering the ds1822 section. recall e 2 [b8h] this command recalls th e alarm trigger values (t h and t l ) and configuration data from eeprom and places the data in bytes 2, 3, and 4, respectively, in the scratchpad memory. the mas ter device can issue read time slots following the recall e 2 command and the ds1822 will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. the recall operation happens automatically at power - up, so valid data is available in the scratchpad as soon as power is applied to the device. read power supply [b4h] the master device issues this command followed by a read time slot to determine if any ds1822s on the bus are using parasite power. during the read time slot, parasite powered ds1822s w ill pull the bus low, and externally powered ds1822s will let the bus remain high. refer to the powering the ds1822 section for usage information for this command. ds1822 function command set table 4 command description protocol 1- wire bus activity after command is issued notes temperature conversion commands convert t initiates temperature conversion. 44h ds1822 transmits conversion status to master (not applicable for parasite -powered ds1822s). 1 memory commands read scratchpad reads the entire scratchpad including the crc byte. beh ds1822 transmits up to 9 data bytes to master. 2 write scratchpad writes data into scratchpad bytes 2, 3, and 4 (t h , t l , and configuration registers). 4eh master transmits 3 data bytes to ds1822. 3 copy scratchpad copies t h , t l , and configuration register data from th e scratchpad to eeprom. 48h none 1 recall e 2 recalls t h , t l , and configuration register data from eeprom to the scratchpad. b8h ds1822 transmits recall status to master. read power supply signals ds1822 power supply mode to the master. b4h ds1822 transmits supply status to master. notes: 1. for parasite - powered ds1822s, the master must enable a strong pullup on the 1 - wire bus during temperature conversions and copies from the scratchpad to eeprom. no other bus activit y may take place during this time. 2. the master can interrupt the transmission of data at any time by issuing a reset. 3. all three bytes must be written before a reset is issued. 12 of 21 downloaded from: http:///
ds1822 rom commands flow chart figure 11 cch skip rom command master t x reset pulse ds1822 t x presence pulse master t x rom command 33h rea d rom command 55h match rom command f0h search rom command ech alarm search command master t x bit 0 ds1822 t x bit 0 ds1822 t x bit 0 master t x bit 0 bit 0 match? master t x bit 1 bit 1 match? bit 63 match? master t x bit 63 n y y y y y n n n n n n n y y y ds1822 t x bit 1 ds1822 t x bit 1 master t x bit 1 ds1822 t x bit 63 ds1822 t x bit 63 master t x bit 63 bit 0 match? bit 1 match? bit 63 match? n n n y y y ds1822 t x family code 1 byte ds1822 t x serial number 6 bytes ds1822 t x crc byte ds1822 t x bit 0 ds1822 t x bit 0 master t x bit 0 n y device(s) with alarm flag set? initialization sequence master t x function command (figure 12) 13 of 21 downloaded from: http:///
ds1822 ds1822 function commands flow chart figure 12 master t x function command y n 44h convert temperature ? parasite pow er ? n y ds1822 begins conversion device converting temperature ? n y master r x 0s master r x 1s master enables strong pullup on dq ds1822 converts temperature master disables strong pullup y n 48h copy scratchpad ? parasite power ? n y master enables strong pull - up on dq data copied from scratchpad to eeprom master disables strong pullup master r x 0s copy in progress ? y master r x 1s n return to initialization sequence (figure 11) for next transaction b4h read power supply ? y n parasite powered ? n master r x 1s master r x 0s y master t x t h byte to scratchpad y n 4eh write scratchpad ? master t x t l byte to scratchpad master t x config. byte to scratchpad y n y beh read scratchpad ? have 8 byt es been read ? n master t x reset ? master r x data byte from scratchpad n y master r x scratchpad crc byte master r x 1s y n b8h recall e 2 ? master begins data recall from e 2 prom device busy recalling data ? n y master r x 0s 14 of 21 downloaded from: http:///
ds1822 1- wire signaling the ds1822 uses a strict 1 - wire communication protocol to insure data integrity. several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. a ll of thes e signals, with the exception of the presence pulse, are initiated by the bus mast er. initialization procedure: reset and presence pulses all communication with the ds1822 begins with an initialization sequence that consi sts of a reset pulse from the mast er followed by a presence pulse from the ds1822. this is illustrated in figure 13. when the ds1822 sends the presence pulse in response to the reset, it is indicating to the ma ster that it is on the bus and ready to operate. during the initialization sequ ence the bus master transmits (t x ) the reset pulse by pulling the 1 - wire bus low for a minimum of 480 s. the bus master then releases the bus and goes into receive mode (r x ). when the bus is released, the 5k pullup resistor pulls the 1 - wire bus high. when the ds1822 detects this rising edge, it waits 15 s to 60 s and then transmits a presence pulse by pulling the 1 - wire bus low for 60 s to 240 s. initialization timing figure 13 read/write time slots the bus master writes data to the ds1822 during write time slots and reads da ta from the ds1822 during read time slots. one bit of data is transmitted over the 1 - wire bus per time slot. write time slots there are two types of write time slots: write 1 time slots and write 0 time slots. the bus master uses a write 1 time slot to write a logic 1 to the ds1822 and a write 0 time slot to write a logic 0 to the ds1822. all write time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual write slots. both types of write time slots are initiated by the ma ster pulling the 1-wire bus low (see figure 14). to generate a write 1 time slot, after pulling the 1 - wire bus low, t he bus master must release the 1 - wire bus within 15 s. when the bus is released, the 5k pullup resistor will pull the bus high. to generat e a write 0 time slot, after pulling the 1 - wire bus low, the bus master must continue to hold the bus low for the dura tion of the time slot (at least 60 s). line type legend bus master pulling low ds1822 pulling low resistor pullup v pu gnd 1- wire bus 480 s minimum 480 s minimum ds1822 t x presence pulse 60 - 240 s master t x reset pulse master r x ds1822 waits 15 - 60 s 15 of 21 downloaded from: http:///
ds1822 the ds1822 samples the 1 - wire bus during a window that lasts from 15 s to 60 s after the master initiates the write time slot. if the bus is high during the sampling window, a 1 is wr itten to the ds1822. if the line i s low, a 0 is written to the ds1822. read/write time slot timing diagram figure 14 read time slots the ds1822 can only transmit data to the master when the master issues read time sl ots. therefore, the master must generate read time slots immediately after issuing a read scratchpad [ beh] or read power supply [ b4h ] command, so that the ds1822 can provide the requested data. in addition, the master can generate read time slots after issuing convert t [44h] or recall e 2 [b8h] co mmands to find out the status of the operation as explained in the ds1822 function command section. all read time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between slots. a read time slot is initiated by the master device pulling the 1 - wire bus low for a minimum of 1 s and then releasing the bus (see figure 14). after the master initiates the r ead time slot, the ds1822 will begin transmitting a 1 or 0 on bus. the ds1822 transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. when transmitting a 0, the ds1822 will release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup res ister. output 45 s 15 s v pu gnd 1- wire bus 60 s < t x 0 < 120 s 1 s < t rec < ds1822 samples min typ max 15 s 30 s > 1 s master write 0 slot master write 1 slot v pu gnd 1- wire bus 15 s master read 0 slot master read 1 slot master samples master samples s tart of slot start of slot > 1 s 1 s < t rec < 15 s 15 s 30 s 15 s ds1822 samples min typ max line type legend bus master pulling low ds1822 pulling low resistor pullup > 1 s 16 of 21 downloaded from: http:///
ds1822 data from the ds1822 is valid for 15 s after the fall ing edge that initiated the read time slot. therefore, the master must release the bus and then sample the bus state within 15 s from the start of the slot. figure 15 illustrates that the sum of t init , t rc , and t sample must be less than 15 s for a read tim e slot. figure 16 shows that system timing margin is maximized by keeping t init and t rc as short as possible and by locating the master sample time during read time slots towards the end of the 1 5 s period. detailed master read 1 timing figure 15 recommended master read 1 timing figure 16 related application notes the following application notes can be applied to the ds1822. these notes can be obtained fr om the dallas semiconductor application note book, via the dallas website at http://www.dalsemi.com/ , or through our faxback service at (214) 450C0441. application note 27: understanding and using cyclic redundancy checks with dallas semiconductor touch memory product application note 55: extending the contact range of touch memories application note 74: reading and writing touch memories via serial interfaces application note 104: minimalist temperature control demo application note 106: complex microlans application note 108: microlan in the long run application note 162: interfacing the ds18x20/ds1822 1 - wire temperature sensor in a microcontroller environment sample 1 - wire subroutines that can be used in conjunction with an74 can be downloaded from the dallas website or anonymous ftp sit e. v pu gnd 1- wire bus 15 s vih of maste r t rc t int > 1 s master samples line type legend bus master pulling low resistor pullup v pu gnd 1- wire bus 15 s vih of master t rc = small t int = small master samples 17 of 21 downloaded from: http:///
ds1822 ds1822 operation example 1 in this example there are multiple ds1822s on the bus and they are using parasite pow er. the bus master initiates a temperature conversion in a specific ds1822 and then reads its scratch pad and recalculates the crc to verify the data. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds1822s respond with presence pulse. tx 55h master issues match rom command. tx 64-bit rom code master sends ds1822 rom code. tx 44h master issues conver t t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence ds1822s respond with presence pulse. tx 55h master issues match rom comman d. tx 64-bit rom code master sends ds1822 rom code. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. ds1822 operation example 2 in this example there is only one ds1822 on the bus and it is using parasite power. the maste r w rites to the t h , t l , and configuration registers in the ds1822 scratchpad and then reads the scratchpad and recalculates the crc to verify the data. the master then copies the scratchpad content s to eeprom. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds1822 responds with presence pulse. tx cch master issues skip rom command. tx 4eh master issues write scratchpad command. tx 3 data bytes master sends three data bytes to scratchpad (t h , t l , and config). tx res et master issues reset pulse. rx presence ds1822 responds with presence pulse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. tx reset master issues reset pulse. rx presence ds1822 responds with presence pulse. tx cch master issues skip rom command. tx 48h master issues copy scratchpad command. tx dq line held high by strong pullup master applies strong pullup to dq for at least 10ms while copy operation is in progress. 18 of 21 downloaded from: http:///
ds1822 absolut e maximum ratings* voltage on any pin relative to ground -0.5v to +6.0v operating temperature range -55 c to +125 c storage temperature range -55 c to +125 c solder dip temperature see ipc/jedec j - std - 020a specification reflow oven temperature +220c *the se are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure t o absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (- 55c to +125c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units notes supply voltage v dd local power +3.0 +5.5 v 1 pullup supply voltage v pu parasite power +3.0 +5.5 v 1, 2 local power +3.0 v dd thermometer error t err -10c to +85c 2 c 3 -55c to +125c 3 input logic low v il -0.3 +0.8 v 1, 4, 5 input logic high v ih local power +2.2 the lower of 5.5 or v dd + 0.3 v 1, 6 parasite power +3.0 sink current i l v i/o =0.4v 4.0 ma 1 standby current i dds 750 1000 na 7, 8 active current i dd v dd =5v 1 1.5 ma 9 dq input current i dq 5 a 10 drift 0.2 c 11 notes: 1. all voltages are referenced to ground. 2. the pullup supply voltage specification assumes that the pullup device is ideal, and the refore the high level of the pullup is equal to v pu . in order to meet the v ih spec of the ds1822, the actual supply rail for the strong pullup transistor must include margin for the voltage drop a cross the transistor when it is turned on; thus: v pu_actual = v pu_ideal + v transistor . 3. see typical performance curve in figure 17. 4. logic low voltages are specified at a sink current of 4ma. 5. to guarantee a presence pulse under low voltage parasite power con ditions, v ilmax may have to be reduced to as low as 0.5v. 6. logic high voltages are specified at a source current of 1ma. 7. standby current specified up to +70 c. standby current typically is 3 a at +125 c. 8. to minimize i dds , dq should be within the following ranges: gnd dq gnd + 0.3v or v dd - 0.3v dq v dd . 9. active current refers to supply current during active temperature conversio ns or eeprom writes. 10. dq line is high (high- z state) . 11. drift data is based on a 1000 hour stress test at +125c with v dd = 5.5v. 19 of 21 downloaded from: http:///
ds1822 ac electrical characteristics: nv memory (- 55c to +100c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units nv write cycle time t wr 2 10 ms eeprom writes n eewr -55c to +55c 50k writes eeprom data retention t eedr -55c to +55c 10 years ac electrical characteristics (- 55c to +125c; v dd = 3.0v to 5.5v) parameter symbol condition min typ max units notes temperature conversion t conv 9- bit resolution 93.75 ms 1 time 10- bit resolution 187.5 ms 1 11- bit resolution 375 ms 1 12- bit resolution 750 ms 1 time to strong pullup on t spon start convert t command issued 10 s time slot t slot 60 120 s 1 recovery time t rec 1 s 1 write 0 low time r low0 60 120 s 1 write 1 low time t low1 1 15 s 1 read da ta valid t rdv 15 s 1 reset time high t rsth 480 s 1 reset time low t rstl 480 s 1,2 presence detect high t pdhigh 15 60 s 1 presence detect low t pdlow 60 240 s 1 capacitance c in/out 25 pf notes: 1. refer to timing diagrams in fig ure 18. 2. under parasite power, if t rstl > 960 s, a power on reset may occur. typical performance curve figure 17 ds1822 typical performance curve -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -10 0 10 20 30 40 50 60 70 80 temperature (c) thermometer error (c) +3s error - 3s error mean error 20 of 21 downloaded from: http:///
ds1822 timing diagrams figure 18 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim prod uct. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 160 rio robles, san jose, ca 95134 408 - 601 - 1000 ? 2015 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. 21 of 21 downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1822ZTR

	To Download DS1822ZTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .